Static random-access memory (SRAM)

How SRAM stores data

An SRAM memory cell commonly uses a small network of transistors arranged as a flip-flop or latch. Typical implementations in complementary metal-oxide-semiconductor (CMOS) processes use four to six transistors per bit cell, creating two stable states that represent logical 0 and 1. Read and write operations access these cells through additional transistors that act as pass gates. The absence of a capacitor-based charge-storage element eliminates the need for refresh circuitry, but cells still consume static power because of leakage currents when powered.

Characteristics and trade-offs

• Speed: SRAM delivers very low latency and high bandwidth, which makes it suitable for timing-critical roles such as CPU caches and register files.
• Volatility: Like other volatile memories, stored data is lost when power is removed.
• Density and cost: Because each bit requires multiple transistors, SRAM is less dense and more expensive per bit than DRAM.
• Power: SRAM does not require refresh cycles, which can save energy at some operating points, but it typically exhibits higher static (leakage) power than DRAM and can be less efficient for very large memories.
• Reliability: SRAM cells are generally stable and fast, though they can be subject to soft errors from energetic particles and to process-related variability in advanced nodes.

History, design and manufacturing

SRAM developed alongside early integrated-circuit memory technologies as designers pursued faster and simpler memory elements for CPUs and digital systems. Modern SRAM circuits are manufactured using standard photolithography and CMOS fabrication techniques. Over decades, cell designs have evolved to balance read stability, writeability, area, and power; the six-transistor (6T) cell is a widely used compromise for many applications. Specialized variants — for example, multiport SRAM for register files or embedded SRAM blocks for system-on-chip designs — adapt the basic cell to different performance and interface requirements.

Primary uses and examples

Because of its speed, SRAM is commonly used where short access time is critical: processor level 1 (L1) and many level 2 (L2) caches, CPU register files, translation lookaside buffers (TLBs), and small on-chip buffers in network equipment. Embedded systems and field-programmable gate arrays (FPGAs) may incorporate SRAM-based memory blocks for fast local storage. In contrast, large main memory arrays are typically implemented with DRAM because it offers higher capacity at lower cost per bit.

Distinctions and notable facts

SRAM is often contrasted with DRAM and nonvolatile memories (such as flash) to highlight trade-offs between speed, cost, density, and persistence. SRAM’s lack of refresh simplifies controller design and can reduce access jitter, which is important in real-time systems. However, its larger silicon area per bit has steered most bulk storage tasks toward DRAM and other technologies. Advances in low-power cell designs and process scaling continue to shape where SRAM is the preferred choice.

Further information and references

• SRAM general reference
• Binary data representation
• Semiconductor device basics
• Volatile vs nonvolatile memory
• Electrical power considerations
• Charge and voltage concepts
• SRAM use in personal computers
• Semiconductor chip technologies
• Photolithography overview
• Transistor counts per SRAM cell
• Flip-flop and latch circuits
• DRAM cell structure
• Capacitor-based storage in DRAM