Instruction cycle (fetch–decode–execute)

Typical stages

Although descriptions vary by architecture, the common high‑level stages are:

• Fetch: Retrieve the next instruction from memory using the program counter.
• Decode: Interpret the instruction bits to determine the operation, operands, and addressing mode.
• Execute: Perform the operation using the arithmetic logic unit, registers, or memory accesses.
• Write-back/Store: Save results to registers or memory and update the program counter for the next instruction.

Internally these steps involve registers such as the program counter (PC), instruction register (IR), memory address/register (MAR/MDR) and various general‑purpose registers.

Variations and enhancements

Real processors implement many refinements. Pipelining overlaps stages of successive instructions to improve throughput. Superscalar designs execute multiple instructions in parallel. Some architectures split decode and execute into more micro‑operations or use microcode to implement complex instructions. Interrupts and exceptions can interrupt the normal cycle and force the control unit to save state and run a handler sequence.

Examples and practical implications

In a simple single‑cycle implementation every instruction completes before the next begins; this is easy to understand but inefficient. Pipelined and out‑of‑order processors are faster but must manage hazards: data dependencies, control flow changes, and resource conflicts. Software designers and compiler writers consider these behaviors when optimizing code to improve locality and reduce stalls.

History and notable facts

The fetch–decode‑execute concept dates to early stored‑program computers. Modern CPUs still follow this logical loop even as designs have grown complex. For further technical detail about processor internals and control logic, see the documentation for the target CPU or architecture family.