Register renaming (computer architecture technique)

How it works

Processors maintain a mapping from architectural registers (the programmer-visible names) to a larger pool of physical registers. During the rename stage of the pipeline a destination register is allocated from the free pool and the mapping table is updated. Subsequent instructions that read that architectural register are directed to the new physical copy. When the renamed value is no longer needed the physical register is returned to the free list.

• Dependencies addressed: Renaming removes false dependencies (write-after-read, anti-dependencies, and write-after-write, output dependencies) but does not remove true read-after-write dataflow dependencies.
• Key structures: register alias table (RAT), physical register file, free list, reorder buffer (ROB) or reservation stations.

Early hardware schemes for eliminating false dependencies include scoreboarding and Tomasulo's algorithm; modern superscalar and out-of-order processors implement register renaming as part of a rename/dispatch stage to enable speculative and parallel execution.

Benefits and trade-offs

Renaming increases instruction-level parallelism and improves pipeline utilization, allowing better performance on workloads with many short-lived register values. Costs include additional silicon for extra physical registers, more complex bookkeeping for precise exceptions and recovery, and potential stalls when the free-list is exhausted.

Register renaming differs from compiler register allocation: compilers assign a limited set of architectural registers to variables at compile time, while hardware renaming dynamically remaps those architectural registers to physical storage at runtime. For further technical treatments see introductory texts and processor design literature: technical overview and implementation case studies in CPU microarchitecture papers (examples of instruction-level concerns).